{"id":9166,"date":"2024-09-03T13:40:00","date_gmt":"2024-09-03T04:40:00","guid":{"rendered":"https:\/\/infosec.pusan.ac.kr\/?page_id=9166"},"modified":"2025-12-23T12:59:42","modified_gmt":"2025-12-23T03:59:42","slug":"sub32","status":"publish","type":"page","link":"https:\/\/infosec.pusan.ac.kr\/index.php\/sub32\/","title":{"rendered":"\ubc18\ub3c4\uccb4 SoC \ubc0f \uc0ac\uc774\ubc84\ubcf4\uc548"},"content":{"rendered":"<p>&nbsp;<\/p>\n<div class=\"sub31\">\n<p><!-- sub tab --><\/p>\n<div class=\"sub_tab\">\n<ul>\n<li><a href=\"index.php\/sub31\">AI\ubcf4\uc548 \ubc0f \uc0b0\uc5c5\uc6a9 AI<\/a><\/li>\n<li><a href=\"index.php\/sub35\">AI\uae30\ubc18 \uc790\uc5f0\uc5b4\ucc98\ub9ac<\/a><\/li>\n<li><a class=\"on\">\ubc18\ub3c4\uccb4SoC \ubc0f \ubcf4\uc548<span class=\"pc840_v\"><\/span><\/a><\/li>\n<li><a href=\"index.php\/sub33\">\ube14\ub85d\uccb4\uc778<span class=\"pc840_v\"><\/span><\/a><\/li>\n<li><a href=\"index.php\/sub34\"><span class=\"pc840_v\">\uc591\uc790\ucef4\ud4e8\ud305 \ubc0f \uc554\ud638 \ud574\ub3c5<\/span><\/a><\/li>\n<li><a href=\"index.php\/port-simulation\">\ud56d\ub9cc \uc2dc\ubbac\ub808\uc774\uc158<\/a><\/li>\n<\/ul>\n<\/div>\n<div class=\"space20\"><\/div>\n<h1>Hardware SOC &amp; Cyber Security<\/h1>\n<div class=\"line6\"><\/div>\n<div class=\"space20\"><\/div>\n<p><!--\n\n\n<blockquote>\n\n\n<h3><a href=\"https:\/\/sec-deadlines.github.io\/\">\ubcf4\uc548 \ubc0f \ud504\ub77c\uc774\ubc84\uc2dc \ucee8\ud37c\ub7f0\uc2a4 \uc77c\uc815\uc548\ub0b4<strong><strong>(<\/strong>Security and Privacy Conference Deadlines)<\/strong><\/a><\/h3>\n\n\n<\/blockquote>\n\n\n\n\n<div class=\"space20\"><\/div>\n\n\n\n\n<div class=\"line6\"><\/div>\n\n\n\n\n<div class=\"space20\"><\/div>\n\n\n--><\/p>\n<div class=\"sub_content_title\">TLS\/SSL(TLS1.2, TLS1.3)\uc9c0\uc6d0 \ubcf4\uc548\uce69 \uac1c\ubc1c \uc5f0\uad6c(Research on TLS Security Chip Optimization and Implementation)<\/div>\n<div class=\"sub_content_txt\">\n<dl>\n<dt>\u2013<\/dt>\n<dd>TLS 1.2 \ubc0f \ubcf4\uc548 \ud45c\uc900 \ud504\ub85c\ud1a0\ucf5c \ud638\ud658 \uce69 FPGA \uad6c\ud604 \ubc0f ASIC(\uacf5\uc815) \uad6c\ud604<\/dd>\n<dt>\u2013<\/dt>\n<dd>\ubcf4\uc548 \uce69\uacfc \uc5f0\ub3d9\uc744 \uc704\ud55c TLS\/SSL \ub77c\uc774\ube0c\ub7ec\ub9ac API(OpenSSL, MbedTLS, WolfSSL, GnuSSL \ub4f1) \uad6c\ud604 \ubc0f \ucd5c\uc801\ud654 \uc5f0\uad6c<\/dd>\n<dt>\u2013<\/dt>\n<dd>CPS(Cyber Physical System) \uc751\uc6a9 \ud504\ub85c\ud1a0\ucf5c(CoAP, MQTT \ub4f1) \ud638\ud658 \uc554\ud638 \ucf54\uc5b4 \ubc0f \uc778\ud130\ud398\uc774\uc2a4 \uac1c\ubc1c<\/dd>\n<dt>\u2013<\/dt>\n<dd>\uc2e4\uc2dc\uac04 \uc81c\uc5b4 \ud504\ub85c\ud1a0\ucf5c(PROFINET, ModBus \ub4f1)\uc758 \ubcf4\uc548\uc131 \uc81c\uacf5\uc744 \uc704\ud55c \uae30\uc220 \uc5f0\uad6c<\/dd>\n<dt>\u2013<\/dt>\n<dd>\uc591\uc790\ub0b4\uc131\uc554\ud638(Post Quantum cryptography) \ucd5c\uc801\ud654 \uad6c\ud604 \ubc0f \uc591\uc790\ub0b4\uc131\uc554\ud638 TLS \ub77c\uc774\ube0c\ub7ec\ub9ac\/CPS \uc751\uc6a9 \ud504\ub85c\ud1a0\ucf5c \uc5f0\ub3d9 \uc5f0\uad6c<\/dd>\n<\/dl>\n<\/div>\n<div class=\"sub_img\">\n<h3><\/h3>\n<div class=\"clear\"><\/div>\n<p><img decoding=\"async\" src=\"https:\/\/infosec.pusan.ac.kr\/wp-content\/uploads\/2023\/04\/figure8.png\" \/><\/p>\n<\/div>\n<div class=\"sub_content_txt\">\n<dl>\n<dt>\u2013<\/dt>\n<dd>\ube14\ub85d \uc554\ud638, \uc2a4\ud2b8\ub9bc \uc554\ud638, \ud0c0\uc6d0\uace1\uc120 \uc554\ud638 \ub4f1 \uc554\ud638 \ubaa8\ub4c8 \uace0\uc18d\ud654\/\ucd5c\uc801\ud654 \ubc0f \ubb3c\ub9ac\ucc44\ub110 \uacf5\uaca9( DPA, CPA, EM Attack, Timing Attack \ub4f1) \ubc29\uc9c0 \uae30\ubc95 \uc5f0\uad6c<\/dd>\n<dt>\u2013<\/dt>\n<dd>HMAC, DRBG, KDF \ub4f1\uc744 \ud65c\uc6a9\ud55c \ud0a4 \uc0dd\uc131 \ud504\ub85c\ud1a0\ucf5c \ubc0f \uc81c\uc5b4 \ubaa8\ub4c8 \uad6c\ud604 \ubc0f \ucd5c\uc801\ud654 \uc5f0\uad6c<\/dd>\n<dt>\u2013<\/dt>\n<dd>CPS(Cyber Physical System) \uc751\uc6a9 \ud504\ub85c\ud1a0\ucf5c(CoAP, MQTT \ub4f1) \ud638\ud658 \uc554\ud638 \ucf54\uc5b4 \ubc0f \uc778\ud130\ud398\uc774\uc2a4 \uac1c\ubc1c<\/dd>\n<dt>\u2013<\/dt>\n<dd>End-To-End \ubcf4\uc548 \ubc0f \uc720\uc120\/\ubb34\uc120 \ub124\ud2b8\uc6cc\ud06c \ubcf4\uc548\uc131\uc744 \uc704\ud55c Layer2 \ubcf4\uc548(MACsec), Layer3 \ubcf4\uc548(IPSec) \ud558\ub4dc\uc6e8\uc5b4 \uad6c\ud604 \ubc0f \uace0\uc18d\ud654 \uae30\ubc95 \uc5f0\uad6c<\/dd>\n<\/dl>\n<\/div>\n<div class=\"space40\"><\/div>\n<div class=\"sub_content_title\">Hardware \uae30\ubc18 \ub525\ub7ec\ub2dd \uac00\uc18d\uae30 \uc5f0\uad6c(Research on Hardware Based Deep Learning Accelerator)<\/div>\n<div class=\"sub_content_txt\">\n<dl>\n<dt>\u2013<\/dt>\n<dd>Real-Time Object Detection Model(Yolo v2, Yolo v4 \ub4f1)\uc5d0 \ub300\ud55c RTL(Register Transfer Level) \uae30\ubc18 \ub525\ub7ec\ub2dd \ucd94\ub860 \uac00\uc18d\ud68c\ub85c Verilog \uad6c\ud604 \ubc0f FPGA\/ASIC \uac1c\ubc1c<\/dd>\n<dt>\u2013<\/dt>\n<dd>\ub525\ub7ec\ub2dd \uac00\uc18d\uae30 \uc785\ub825 \ub370\uc774\ud130(Image Data, Weight Data)\uc5d0 \ub300\ud55c \ub370\uc774\ud130 \uc804\ucc98\ub9ac(Fixed Point, Dynamic Fixed Point, Round up \uae30\ubc95, Floating Point \uc5f0\uc0b0\uae30 \ucd5c\uc801\ud654 \ub4f1) \ubc0f \uac1d\uccb4 \ud0d0\uc9c0 \uacb0\uacfc(Bounding box, Class) \ub370\uc774\ud130 \ud6c4\ucc98\ub9ac \uae30\ubc95 \uc5f0\uad6c<\/dd>\n<dt>\u2013<\/dt>\n<dd>BNN(Binarized Neural Network) \uae30\ubc18 \ucd94\ub860 \uc5f0\uc0b0 \uac00\uc18d \ud68c\ub85c Verilog \uad6c\ud604 \ubc0f \ud638\uc2a4\ud2b8 \ud504\ub85c\uc138\uc11c\uc640\uc758 \uc5f0\ub3d9\uc744 \ud1b5\ud55c System On Chip \uac1c\ubc1c<\/dd>\n<dt>\u2013<\/dt>\n<dd>\uc678\ubd80 \uba54\ubaa8\ub9ac \uc800\uc7a5 \ud30c\ub77c\ubbf8\ud130\uc5d0 \ub300\ud55c DRAM \ud0c0\uac9f \uacf5\uaca9(Bit Flip Attack, Code Corruption Attack, EM Attack \ub4f1) \ubc29\uc5b4 \uae30\ubc95(\ub370\uc774\ud130 \ubb34\uacb0\uc131 \ubc0f \uae30\ubc00\uc131 \ubcf4\uc7a5 \uad6c\uc870) \uc5f0\uad6c<\/dd>\n<dd><\/dd>\n<\/dl>\n<\/div>\n<div class=\"sub_img\">\n<h3>[\ub525\ub7ec\ub2dd \uac00\uc18d\uae30 \uc124\uacc4 \uad6c\uc870]<\/h3>\n<div class=\"clear\"><\/div>\n<p><img decoding=\"async\" src=\"https:\/\/infosec.pusan.ac.kr\/wp-content\/uploads\/2022\/12\/figure7.png\" \/><\/p>\n<\/div>\n<div class=\"sub_img\">\n<h3>[\ub0b4\ubd80 \uba54\ubaa8\ub9ac \uc2a4\ucf00\uc904\ub9c1 \uae30\ubc95 \ucd5c\uc801\ud654 \uc5f0\uad6c]<\/h3>\n<div class=\"clear\"><\/div>\n<p><img decoding=\"async\" src=\"https:\/\/infosec.pusan.ac.kr\/wp-content\/uploads\/2022\/12\/figure8.png\" \/><\/p>\n<\/div>\n<div class=\"sub_content_txt\">\n<dl>\n<dt>\u2013<\/dt>\n<dd>\ub525\ub7ec\ub2dd \uac00\uc18d\uae30\uc5d0 \ub300\ud55c \ubb3c\ub9ac\ucc44\ub110 \uacf5\uaca9(Power Analysis, Timing Attack, Glitch Attack \ub4f1) \ubc29\uc5b4 \uae30\ubc95 \uc5f0\uad6c<\/dd>\n<dt>\u2013<\/dt>\n<dd>\ub525\ub7ec\ub2dd \uac00\uc18d\uae30 \uba54\ubaa8\ub9ac \uc2a4\ucf00\uc904\ub9c1 \ucd5c\uc801\ud654(Line based Reuse, Hybrid Reuse) \uae30\ubc95 \uc5f0\uad6c<\/dd>\n<dt>\u2013<\/dt>\n<dd>Binarized Layer \uc5f0\uc0b0\uae30 \ucd5c\uc801\ud654 \uae30\ubc95(Logic Gate \uae30\ubc18 Binarized Convolution Method, Bit Shift \uae30\ubc18 Batch Normalization \ub4f1) \uc5f0\uad6c<\/dd>\n<\/dl>\n<\/div>\n<div class=\"space40\"><\/div>\n<div class=\"sub_content_title\">\uc2dc\uc2a4\ud15c \uad6c\uc870(RISC-V, ARM, Intel) \ubc0f \ubcf4\uc548 \uc5f0\uad6c(Research on System Architecture and Security)<\/div>\n<div class=\"sub_content_txt\">\n<dl>\n<dt>\u2013<\/dt>\n<dd>\uc800\uc0ac\uc591 \ubc0f \uc784\ubca0\ub514\ub4dc \ub514\ubc14\uc774\uc2a4\ub97c \uc704\ud55c 32-bit\/64-bit \ucf54\ud504\ub85c\uc138\uc11c(Coprocessor) \uad6c\uc870 \uc124\uacc4 \ubc0f \uac1c\ubc1c \uc5f0\uad6c<\/dd>\n<dt>\u2013<\/dt>\n<dd>\uba85\ub839\uc5b4 \ud30c\uc774\ud504\ub77c\uc778 \ucd5c\uc801\ud654 \uc5f0\uad6c(Out-Of-Order Completion) \ubc0f \uba85\ub839\uc5b4 \ud655\uc7a5(Vector Processing Unit) \uc5f0\uad6c<\/dd>\n<dd><\/dd>\n<\/dl>\n<\/div>\n<div class=\"sub_img\">\n<h3>[\uba85\ub839\uc5b4 \ud30c\uc774\ud504\ub77c\uc778 \ucd5c\uc801\ud654 \uc5f0\uad6c]<\/h3>\n<div class=\"clear\"><\/div>\n<p><img decoding=\"async\" src=\"https:\/\/infosec.pusan.ac.kr\/wp-content\/uploads\/2022\/12\/figure9.png\" \/><\/p>\n<\/div>\n<div class=\"sub_content_txt\">\n<dl>\n<dt>\u2013<\/dt>\n<dd>ARIA-GCM \ubc0f HMAC \uae30\ubc18 \uba54\ubaa8\ub9ac \uaca9\ub9ac(\ubb34\uacb0\uc131\/\uae30\ubc00\uc131 \ubcf4\uc7a5) \uae30\uc220 \uc5f0\uad6c(\ud0a4, IV \ub4f1 \ud30c\ub77c\ubbf8\ud130 \ubcf4\ud638 \uae30\ubc95, \ucd08\uae30\ud654 \ubc0f \uc778\ud130\ud398\uc774\uc2a4 \ucc28\ub2e8 \ub4f1)<\/dd>\n<dt>\u2013<\/dt>\n<dd>RISC-V ISA(Instruction Set Architecture) \ubc0f PMP(Physical Memory Protection)\ub97c \ud65c\uc6a9\ud55c \uba85\ub839\uc5b4 \uc218\uc900\uc758 \ub3c4\uba54\uc778 \uaca9\ub9ac(Domain Isolation) \ubc0f TMA(Tagged Memory Architecture)\uae30\uc220 \uc5f0\uad6c<\/dd>\n<dd><\/dd>\n<\/dl>\n<\/div>\n<div class=\"sub_img\">\n<h3>[\uba85\ub839\uc5b4 \uc218\uc900\uc758 \ub3c4\uba54\uc778 \uaca9\ub9ac \uae30\uc220 \uc5f0\uad6c]<\/h3>\n<div class=\"clear\"><\/div>\n<p><img decoding=\"async\" src=\"https:\/\/infosec.pusan.ac.kr\/wp-content\/uploads\/2022\/12\/figure10.png\" \/><\/p>\n<\/div>\n<div class=\"sub_img\"><\/div>\n<\/div>\n<div class=\"clear\">\n<div class=\"sub_content_title\">KCMVP Security Level 3\uc6a9 \ubcf4\uc548\uce69 \uac1c\ubc1c \ubc0f Tamper Resistence \uae30\uc220 \uc5f0\uad6c<\/div>\n<div class=\"sub_content_txt\">\n<dl>\n<dt>\u2013<\/dt>\n<dd>Security Level 3\ub97c \uac16\ub294 \uace0\ubcf4\uc548\uc131 \ud558\ub4dc\uc6e8\uc5b4 \ubcf4\uc548 \ubaa8\ub4c8 \ud575\uc2ec \uae30\uc220 \uc5f0\uad6c<\/dd>\n<dt>\u2013<\/dt>\n<dd>Tamper Resistence, Tamper Evidence \uae30\uc220 \uc5f0\uad6c<\/dd>\n<\/dl>\n<h3>[Security Level 3 \uc774\uc0c1\uc758 \uace0\ubcf4\uc548\uc131 \ud558\ub4dc\uc6e8\uc5b4 \ubcf4\uc548 \ud575\uc2ec \uae30\uc220 \uc5f0\uad6c]<\/h3>\n<\/div>\n<\/div>\n<div>\n<div class=\"sub_img\">\n<p style=\"text-align: left;\">\u2013HSM(Hardware Security Modeul), TPM(Trusted Platform Module)\uc5d0\uc11c\ucc98\ub7fc, \ub192\uc740 \ubcf4\uc548\uc131\uc744 \uac16\ub294 \ud0a4 \uad00\ub9ac \uae30\uc220 \uc5f0\uad6c \ud544\uc694<\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: left;\">\u2013\ubd80\ucc44\ub110 \uacf5\uaca9(Side-channel Attack) \uc800\ud56d\uc131 \uc81c\uacf5 \ud544\uc694 (Timing attack, SPA\/DPA \uacf5\uaca9 \ub300\uc751 \uae30\uc220 \ubcf4\uc720 \ud544\uc694)<\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: left;\">\u2013\ub192\uc740 \uc5d4\ud2b8\ub85c\ud53c \uac12\uc744 \uac16\ub294 \uc554\ud638\ud0a4(\ube44\ubc00\uc815\ubcf4) \uc0dd\uc131 \uae30\uc220 \ud544\uc694<\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: left;\">\u2013\uc790\uaca9 \uae30\ubc18 \uc8fc\uc694 \uae30\ub2a5\/\ub370\uc774\ud130 \uc811\uadfc \uc81c\uc5b4 \uae30\uc220 \uc81c\uacf5 \ud544\uc694<\/p>\n<\/div>\n<\/div>\n<div><\/div>\n<div>\n<h3>[Security Level 3\ub97c \uc704\ud55c Tamper Resistance, Tamper Evidence \uae30\uc220 \uc5f0\uad6c]<\/h3>\n<div>\n<p>\u2013\ubb3c\ub9ac\uc801 Tamper Resistance \uae30\uc220\ub85c\ub294 \ubb3c\ub9ac\uc801 \ubcf4\uc548 \uac15\ud654(\ud2b9\uc218 \ucf00\uc774\uc2a4, \ud640\ub85c\uadf8\ub7a8 \uc2a4\ud2f0\ucee4, \uac1c\ubd09 \uc5ec\ubd80 \ud655\uc778 \uc2a4\ud2f0\ucee4, eSeal \ub4f1) \uae30\uc220 \ubc0f \uc218\ub2e8 \uc874\uc7ac\ud568<\/p>\n<p>&#8211;<\/p>\n<p>\ub17c\ub9ac\uc801 Tamper Resistance \uae30\uc220\ub85c\ub294 S\/W \ubb34\uacb0\uc131 \uac80\uc99d, \ubcf4\uc548 \ubd80\ud305, eSeal, Isolation\/Segmentation \ub4f1, \ub2e4\uc591\ud55c \uae30\uc220\uc774 \uc874\uc7ac\ud560 \uc218\u00a0 \uc788\uc74c<\/p>\n<p>&#8211;<\/p>\n<p>Tamper Resistance \uae30\uc220\uc740 \uce68\uc785\ud0d0\uc9c0 \uc13c\uc11c\ub098 \ubb3c\ub9ac\uc801 \uc190\uc0c1 \uc5ec\ubd80 \ud655\uc778 \uc7a5\uce58(\ud640\ub85c\uadf8\ub7a8 \uc2a4\ud2f0\ucee4 \ub4f1), \ub17c\ub9ac\uc801 \uce68\uc785 \ud0d0\uc9c0 \uae30\uc220\uc744 \uae30\ubc18\uc73c\ub85c\ud558\ub294 Tamper Evidence \uae30\uc220\uacfc \ud568\uaed8 \uc0ac\uc6a9\ub418\uc5b4, \uadf8 \ubcf4\uc548\uc131\uc744 \ub192\uc784<\/p>\n<\/div>\n<div><\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p>&nbsp; AI\ubcf4\uc548 \ubc0f \uc0b0\uc5c5\uc6a9 AI AI\uae30\ubc18 \uc790\uc5f0\uc5b4\ucc98\ub9ac \ubc18\ub3c4\uccb4SoC \ubc0f \ubcf4\uc548 \ube14\ub85d\uccb4\uc778 \uc591\uc790\ucef4\ud4e8\ud305 \ubc0f \uc554\ud638 \ud574\ub3c5 \ud56d\ub9cc \uc2dc\ubbac\ub808\uc774\uc158 Hardware SOC &amp; Cyber Security TLS\/SSL(TLS1.2, TLS1.3)\uc9c0\uc6d0 \ubcf4\uc548\uce69 \uac1c\ubc1c \uc5f0\uad6c(Research on TLS Security Chip Optimization and Implementation) \u2013 TLS 1.2 \ubc0f \ubcf4\uc548 \ud45c\uc900 \ud504\ub85c\ud1a0\ucf5c \ud638\ud658 \uce69 FPGA \uad6c\ud604 \ubc0f ASIC(\uacf5\uc815) \uad6c\ud604 \u2013 \ubcf4\uc548 \uce69\uacfc \uc5f0\ub3d9\uc744 \uc704\ud55c TLS\/SSL \ub77c\uc774\ube0c\ub7ec\ub9ac [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"page-sub3.php","meta":{"footnotes":""},"class_list":["post-9166","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/infosec.pusan.ac.kr\/index.php\/wp-json\/wp\/v2\/pages\/9166","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/infosec.pusan.ac.kr\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/infosec.pusan.ac.kr\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/infosec.pusan.ac.kr\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/infosec.pusan.ac.kr\/index.php\/wp-json\/wp\/v2\/comments?post=9166"}],"version-history":[{"count":9,"href":"https:\/\/infosec.pusan.ac.kr\/index.php\/wp-json\/wp\/v2\/pages\/9166\/revisions"}],"predecessor-version":[{"id":9543,"href":"https:\/\/infosec.pusan.ac.kr\/index.php\/wp-json\/wp\/v2\/pages\/9166\/revisions\/9543"}],"wp:attachment":[{"href":"https:\/\/infosec.pusan.ac.kr\/index.php\/wp-json\/wp\/v2\/media?parent=9166"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}